1. Field of the Invention
The present invention relates to a phase locked loop (hereinafer, referred to as "PLL"), and more particularly, to a PLL for recovering a clock.
2. Discussion of Related Art
Generally, an apparatus for recovering a clock is requisite for a digital magnetic recording equipment or a digital communication system. In this case, of course, the clock recovering operation of the apparatus is very important for the normal operation of the equipment or system.
As well known, a PLL as the apparatus for recovering a clock is widely used.
Now, an explanation of the construction of a conventional PLL will be discussed with reference to FIGS. 1 and 2.
FIG. 1 is a circuit diagram illustrating the construction of a conventional PLL. As shown, the PLL is comprised of a phase detector 10 for comparing the phase of a reference input signal and the phase of a feedback signal, a loop filter 20 for filtering the phase of an output signal from the phase detector 10 and for eliminating a high frequency component of the filtered signal to thereby output a predetermined voltage of signal, and a voltage controlled oscillator (hereinafter, referred to as "VCO") 30 for generating a predetermined frequency in accordance with the voltage of the output signal from the loop filter 20.
FIG. 2 is a detailed circuit diagram of the phase detector 10 in FIG. 1. The phase detector 10 includes a first D flip-flop 11 for delaying the reference input signal during a predetermined period of time to thereby output the delayed signal, a second D flip-flop 12 for delaying the feedback signal of the output signal from the VCO 30 during a predetermined period of time to thereby output the delayed signal, and an exclusive OR gate 13 for exclusively ORing the output signals of the first and second D flip-flops 11 and 12 to thereby output the ORed signal.
FIG. 3 is a graph illustrating a signal transmitting characteristic of the phase detector 10 of FIG. 2, and FIGS. 4A to 4C are waveform diagrams illustrating output states of the components of the conventional PLL, in the case where a phase difference between the reference input signal to the phase detector 10 and the output signal of the VCO 30 corresponds to .PI. radian.
FIGS. 5A to 5C are waveform diagrams illustrating output states of the components of the conventional PLL, in the case where the phase of the reference input signal to the phase detector 10 precedes the phase of the output signal of the VCO 30, on the basis of the .PI. radian. FIGS. 6A to 6C are waveform diagrams illustrating output states of the components of the conventional PLL, in the case where the phase of the reference input signal to the phase detector 10 is behind the phase of the output signal of the VCO 30, on the basis of the .PI. radian. FIGS. 7A to 7D are waveform diagrams illustrating output states of the components of the conventional PLL, in the case where the period of the reference input signal to the phase detector 10 is irregular and a part of a pulse column of the signal is omitted.
Next, an explanation of the operation of the conventional PLL will be discussed with reference to FIG. 3 to FIGS. 7A to 7D.
Firstly, the phase detector 10 compares the phases between the reference input signal and the feedback signal from the output signal of the VCO 30 and outputs the compared result.
In more detail, the first D flip-flop 11 of the phase detector 10 delays the reference input signal `a` during the predetermined period of time to thereby output the delayed signal, as shown in FIG. 2.
On the other hand, the second D flip-flop 12 of the phase detector 10 delays the feedback signal `b` of the output signal from the VCO 30 during the predetermined period of time to thereby output the delayed signal.
As a result, the exclusive OR gate 13 of the phase detector 10 exclusively ORes the output signals of the first and second D flip-flops 11 and 12 to thereby output the ORed signal `c`.
The output signal `c` of the phase detector 10 has a linear characteristic in the range of 2.PI. radian, as shown in FIG. 3.
Next, the loop filter 20 filters the phase of the output signal `c` from the phase detector 10 and eliminates a high frequency component of the filtered signal to thereby output a predetermined voltage of signal. Then, the VCO 30 generates a predetermined frequency in accordance with the voltage of the output signal from the loop filter 20 and then outputs a recovered clock.
Now, an explanation of the operation of the phase detector 10 of the conventional PLL will be in detail given.
Firstly, in the case where a phase difference between the reference input signal `a` to the phase detector 10 and the output signal `b` of the VCO 30 corresponds to .PI. radian, the first D flip-flop 11 delays and outputs the reference input signal `a` as the waveform shown in FIG. 4A during the predetermined period of time. Also, the second D flip-flop 12 delays and outputs the feedback signal `b` of the output signal from the VCO 30 as the waveform shown in FIG. 4B during the predetermined period of time. As a result, the exclusive OR gate 13 of the phase detector 10 exclusively ORes the output signals of the first and second D flip-flops 11 and 12 to thereby output the ORed signal `c` as the waveform shown in FIG. 4C.
At this time, if a direct current (DC) voltage outputted from the exclusive OR gate 13 is detected, it can be noted that the DC voltage has an intermediate value of the waveform as shown in FIG. 4C.
Secondly, in the case where the phase of the reference input signal `a` to the phase detector 10 precedes the phase of the output signal `b` of the VCO 30, on the basis of the .PI. radian, the first D flip-flop 11 delays and outputs the reference input signal `a` as the waveform shown in FIG. 5A during the predetermined period of time. Also, the second D flip-flop 12 delays and outputs the feedback signal `b` of the output signal from the VCO 30 as the waveform shown in FIG. 5B during the predetermined period of time. As a result, the exclusive OR gate 13 of the phase detector 10 exclusively ORes the output signals of the first and second D flip-flops 11 and 12 to thereby output the ORed signal `c` as the waveform shown in FIG. 5C.
At this time, if the DC voltage outputted from the exclusive OR gate 13 is detected, it can be noted that the DC voltage has a value higher than the intermediate value of the waveform as shown in FIG. 5C.
Thirdly, in the case where the phase of the reference input signal `a` to the phase detector 10 is behind the phase of the output signal `b` of the VCO 30, on the basis of the .PI. radian, the first D flip-flop 11 delays and outputs the reference input signal `a` as the waveform shown in FIG. 6A during the predetermined period of time. Also, the second D flip-flop 12 delays and outputs the feedback signal `b` of the output signal from the VCO 30 as the waveform shown in FIG. 6B during the predetermined period of time. As a result, the exclusive OR gate 13 of the phase detector 10 exclusively ORes the output signals of the first and second D flip-flops 11 and 12 to thereby output the ORed signal `c` as the waveform shown in FIG. 6C.
At this time, if the DC voltage outputted from the exclusive OR gate 13 is detected, it can be noted that the DC voltage has a value lower than the intermediate value of the waveform as shown in FIG. 6C.
Finally, in the case where the period of the reference input signal `a` to the phase detector 10 is irregular and a part of a pulse column of the signal is omitted, the first D flip-flop 11 delays and outputs the reference input signal `a` as the waveform shown in FIG. 7A during the predetermined period of time. Also, the second D flip-flop 12 delays and outputs the feedback signal `b` of the output signal from the VCO 30 as the waveform shown in FIG. 7B during the predetermined period of time. As a result, the exclusive OR gate 13 of the phase detector 10 exclusively ORes the output signals of the first and second D flip-flops 11 and 12 to thereby output the ORed signal `c` as the waveform shown in FIG. 7C.
At this time, if the DC voltage outputted from the exclusive OR gate 13 is detected, it can be noted that the DC voltage has an intermediate value of the waveform as shown in FIG. 7C.
The loop filter 20 filters the phase of the output signal `c` from the phase detector 10 and eliminates the high frequency component of the filtered signal to thereby output a predetermined voltage of signal, as shown in FIG. 7D. As known from FIG. 7D, the DC voltage within the area of "A" is below the intermediate value of the DC voltage. Accordingly, the VCO 30 fails to maintain a center frequency as shown in FIG. 3 and thus produces frequency deviation in one-sided direction, which results in generation of a timing error.
Hence, the conventional PLL contains a problem to be solved that in the case where a part of the pulse column of the reference input signal does not exist, since the VCO can not maintain the center frequency and thus generates the frequency deviation in the one-sided direction, a timing error inevitably occurs.